MISFET including GaAs substrate and a Group II-VI gate insulator

ABSTRACT

A MISFET includes a GaAs substrate, a gate insulating film of a II-VI group compound including Zn, Mg, S, and Se epitaxially grown on the GaAs substrate, and a gate electrode formed on the gate insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a MIS (Metal Insulator Semiconductor)FET (Field Effect Transistor), and more particularly, to an improvementof a MISFET including a GaAs substrate.

2. Description of the Background Art

Logical elements utilizing a GaAs-MES (Metal Semiconductor) FET or aGaAs-J (Junction) FET had a problem that the logic voltage swing couldnot be increased, because an increase in logic voltage swing will causeforward current to flow via a gate junction. If a GaAs-MISFET is used,the aforementioned problem will not occur, logically, because the gateelectrode is insulated by a gate insulating film, allowing the formationof a high speed logical element that can permit to a great logic voltageswing. The usage of a GaAs-MISFET also allows the formation of a highfrequency analog element that can have a signal with a large voltageswing applied to the gate electrode.

FET is known

In the conventional art, a GaAs-MISFET is known including a gateinsulating film made of a material such as SiO₂, SiN_(x), or CaF₂ formedon a GaAs substrate by thermal CVD (Chemical Vapor Deposition),plasma-enhanced CVD, photo CVD, or sputtering, and a gate electrodeformed thereabove. However, the use of SiO₂, SiN_(x), or CaF₂ as a gateinsulating film cause an undesired increase in interface state densityon account of the interface structure between the gate insulating filmand the GaAs substrate being disturbed. It was therefore difficult tomanufacture a practical GaAs-MISFET.

A pseudo-MISFET is known in the conventional art using an undoped A(GaAsfilm formed on a GaAs substrate by the MBE (Molecular Beam Epitaxy)deposition method or by the MO (Metal Organic) CVD method substituting agate insulating film. Although this pseudo-MISFET has a good gateinterface with a low interface state density, the AlGaAs film does notestablish complete lattice matching with the GaAs substrate. Anotherdisadvantage is that the band offset between the valance band of thegate insulating film and the valence band of the GaAs substrate (i.e.,an energy barrier) can not be increased because of the insufficientenergy band gap in the AlGaAs film. It was therefore difficult torealize a p channel MISFET.

A MISFET is known in the conventional art using a II-VI group compoundsemiconductor such as ZnS, ZnSe, or ZnSSe as a gate insulating film.Although ZnS and ZnSe both do not establish lattice matching with a GaAssubstrate, the lattice constant of ZnSe is close to that of GaAs toallow a good gate interface by reducing significantly the thickness ofthe ZnSe film. Furthermore, if the ternary compound ZnSSe is used as agate insulating film, lattice matching can be obtained between the gateinsulating film and the GaAs substrate in the composition of ZnS₀.06Se₀.94 to result in a good gate interface. These II-VI group compoundsemiconductors have a relatively great energy band gap.

However, the band offset amount at the conduction band side between thegate insulating film formed of the aforementioned II-VI group compoundsemiconductor and the GaAs substrate can not be increased, so that theaforementioned II-VI group compound semiconductors are not practical asa gate insulating film in a GaAs-MISFET.

The GaAs-MISFET of the conventional art had the problems of undesiredhigh interface energy level between the interface of a gate insulatingfilm and a GaAs substrate and insufficient band offset. A practicalGaAs-MISFET was not yet obtained.

SUMMARY OF THE INVENTION

In view of the foregoing, an object of the present invention is toprovide a practical MISFET having a low interface energy level densityand a great band offset between a gate insulating film and a GaAssubstrate.

A MISFET according to the present invention includes a GaAs substrate, agate insulating film of a II-VI group compound semiconductor includingZn, Mg, S, and Se on the GaAs substrate, and a gate electrode formed onthe gate insulating film.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of a MISFET according to anembodiment of the present invention.

FIG. 2 is a diagram illustrating the electronic energy state in thevicinity of the interface region of a GaAs substrate and a gateinsulating film.

FIG. 3 is a diagram illustrating another electronic energy state in thevicinity of the interface between a GaAs substrate and a gate insulatingfilm.

FIG. 4 is a graph showing the relationship of the II-VI group compoundsemiconductor Zn_(1-x) Mg_(x) S_(y) Se_(1-y) composition and energy bandgap Eg (eV).

FIG. 5 is a graph showing the energy band gaps of GaAs, ZnS, ZnSe, MgS,and MgSe calculated by the approximation of Harrison's LCAO (LinearCombination of Atomic Orbitals).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a GaAs-MISFET according to an embodiment of thepresent invention will be described hereinafter. In this MISFET 1, a p⁻-GaAs layer 3 is formed on a semi-insulating GaAs substrate 2 byepitaxial growth or ion implantation. The semi-insulating GaAs substrate2 and the p⁻ -GaAs layer 3 are referred to as a GaAs substrate 4hereinafter. Above the GaAs substrate 4, a gate insulating film 5 of aII-VI group compound semiconductor Zn_(1-x) Mg_(x) S_(y) Se_(1-y) isformed by the MOCVD method or the MBE method. An n⁺ source region 6 andan n drain region 7 are formed at the sides of the gate insulating film5 by means of ion implantation or thermal diffusion of n-type dopantsinto the p⁻ -GaAs layer 3. A source electrode 8 and a drain electrode 9are formed on the source region 6 and the drain region 7, respectively.A gate electrode 10 is formed on the gate insulating film 5. TheGaAs-MISFET of FIG. 1 is an inversion type MISFET that operates byinducing carriers in the interface of the GaAs substrate 4 and the gateinsulating film 5.

The II-VI group compound semiconductor Zn_(1-x) Mg_(x) S_(y) Se_(1-y)composition available as a gate insulating film of the n channel typeMISFET of FIG. 1 must be set to satisfy the following three conditions.

Condition 1: The gate insulating film must have a required amount ofband offset ΔEc (the height of the energy barrier between the conductionband of the gate insulating film and the conduction band of the GaAssubstrate) with respect to the conduction band of the GaAs substrate(refer to FIG. 2), in order to prevent the carriers (electrons) on thesurface of the GaAs substrate from passing over the gate insulating filmby thermal energy.

Condition 2: Carriers must not pass through the gate insulating film asa result of a tunneling effect under the requirements of generating astrong inversion at the surface of the GaAs substrate.

Condition 3: Carriers must not pass through the gate insulating film asa result of a tunneling effect even when a voltage of 5 volts accordingto the usual TTL (Transistor Transistor Logic) level is applied to thegate electrode as the maximum value of the MISFET gate driving voltage(refer to FIG. 3).

Because the MISFET is designed to have the surface of the GaAs substrateheavily inverted when a voltage of 5 volts is applied to the gateelectrode, condition 2 will inevitably be satisfied if condition 3 ismet. Thus the composition of Zn_(1-x) Mg_(x) S_(y) Se_(1-y) should beestablished to satisfy conditions 1 and 3.

The amount of band offset is now considered. Although the band offsetamount ΔEc between the conduction bands of the gate insulating film andthe GaAs substrate depends upon the composition of the gate insulatingfilm, the band offset amount ΔEc must be greater than the minimum valueof ΔEc_(min) which is determined by the above described threeconditions. The more the band offset amount ΔEc is greater than theminimum value ΔEc_(min), the more preferable ΔEc is. In order toincrease the band offset amount ΔEc, the ratio of Mg in Zn_(1-x) Mg_(x)S_(y) SE_(1-y) should be increased. If the ratio of Mg is excessivelyincreased, the gate insulating film will easily have a rock salt typecrystal structure, making it difficult to grow a gate insulating film ofgood quality on the GaAs substrate. Therefore, the maximum valueΔEc_(max) of the band offset amount ΔEc must be set to an appropriatevalue.

The minimum value ΔEc_(min) and the maximum value ΔEc_(max) of the bandoffset amount ΔEc are determined taking into consideration conditions 1and 3 and the nature of the gate insulating film. Although the p⁻ -GaAslayer in the GaAs substrate is assumed to have a hole density of 10¹⁶/cm³ in room temperature in the following, the hole density is notlimited to this value.

First, condition 1 is considered. Referring to FIG. 2 where carriers(electrons) 11 travel beyond the barrier of the band offset ΔEc byvirtue of the thermal energy at a temperature of T (=300° K), thefollowing equation (1) must be satisfied to suppress the number ofcarriers going beyond the barrier to be not more than 1% of theaccumulated carriers.

    exp (-ΔEc/kT)<0.01                                   (1)

where k represents Boltzmann's constant. More specifically, ΔEc isexpressed by the following equation (2).

    ΔEc>4.6kT=0.12eV                                     (2)

Next, condition 3 is considered. FIG. 3 shows the energy state whenvoltage V is applied to the gate electrode to generate a stronglyinverted layer 12 at the surface of the GaAs substrate. In FIG. 3, φsrepresents the surface potential required to invert strongly the surfaceof the GaAs substrate, and L represents the tunneling distance thecarriers 11 pass through. Here, the electric field Ei in the gateinsulating film is represented by the following equation (3).

    Ei=(V-φs) / di                                         (3)

where di represents the thickness of the gate insulating film. Althoughthe surface potential φs required to invert strongly the surface of theGaAs substrate is calculated as φs=1.16eV at the initiation of theinversion, φs becomes slightly greater than 1.16eV at the stronglyinverted state where voltage V is applied. Hence, by assuming that thesurface potential φs when voltage V=5 volts is applied is 1.3eVincluding some allowance, the electric field Ei in the gate insulatingfilm is expressed as the following equation (4).

    Ei=(5-1.3) / di=3.7 /di                                    (4)

When the hole density is 10¹⁶ /cm³ in the GaAs substrate, the electricfield Es at the surface of the GaAs substrate at the initiation of thestrong inversion is expressed by the following equation (5).

    Es=5.7×10.sup.4 V/cm                                 (5)

According to Gauss's law, the electric field Ei of the gate insulatingfilm at the state of heavy inversion is expressed as the followingequation (6).

    Ei≳εs·Es / εi=1.3×10.sup.5 V/cm(6)

where εs and εi represent the dielectric constants of the GaAs substrateand the gate insulating film, respectively. In equation (6), thedielectric constant of ZnSe is used as εi.

Therefore, the following equation (7) is obtained by equations (4) and(6).

    di≲2900Å                                       (7)

The thickness di of the gate insulating film must be not more than 2900Åin order to reliably generate a strong inversion layer by a 5 volts gatevoltage application.

The allowable minimum ΔEc_(min) of the band offset amount ΔEc of theconduction band is determined as the minimum value that can maintain atunneling probability within a negligible range in the film thicknessdi. The tunneling distance L is expressed as L=ΔEc / Ei, whereby thefollowing equation (8) is obtained using equation (4).

    L=ΔEc·di / 3.7                              (8)

The tunneling probability can substantially be neglected if L=100Å,whereby the following equation (9) can be obtained from equation (8).

    ΔEc≳3.7×L / di=0.13eV                  (9)

Because equation (2) is obtained from condition 1, the minimum valueΔEc_(min) of ΔEc satisfying both the equations of (2) and (9) isexpressed by the following equation (10).

    ΔEc.sub.min= 0.13eV                                  (10)

Regarding the maximum value ΔEc_(max) of the band offset amount ΔEc,only condition 3 needs to be considered because condition 3 is morecritical than condition 1. With L=100Å as the tunneling distance anddi=400Å as the thickness of the gate insulating film, the followingequation (11) can be obtained from equation (8).

    ΔEc.sub.max= 3.7×100 / 400=0.93eV              (11)

As mentioned above, it is preferred that the band offset amount ΔEc isas great as possible. However, if the ratio of Mg in the gate insulatingfilm is increased in order to bring the band offset amount ΔEc greaterthan the maximum value ΔEc_(max), the gate insulating film is morelikely to have a rock salt type crystal structure. It will therefore bedifficult to grow the crystal of the gate insulating film on the GaAssubstrate.

Thus, the following equation (12) must be satisfied for a MISFET tooperate in practice.

    0.13eV≲ΔEc≲0.93eV                    (12)

Therefore, the composition ratio of X and Y in Zn_(1-x) Mg_(x) S_(y)Se_(1-y) is determined to obtain a band offset amount ΔEc within therange of equation (12).

FIG. 4 shows the relation ship between the composition of II-VI groupcompound semiconductor Zn_(1-x) Mg_(x) S_(y) Se_(1-y) and the band gapEg. The abscissa represents the composition ratio of x and the ordinaterepresents the composition ratio of y. Curves 13 represent the contourline of the band gap Eg, and the value on each contour line representsthe corresponding band gap Eg in the unit of eV. The slanted straightline 14 in FIG. 4 represents the composition of Zn_(1-x) Mg_(x) S_(y)Se_(1-y) having a lattice constant identical to that of GaAs, which willbe referred to as an "equivalent lattice constant line" hereinafter.This equivalent lattice constant line 14 corresponds substantially tothe direction from ZnSe (x=1, y=0) towards MgS (x=0, y=1). Morespecifically, the equivalent lattice constant line 14 runs from point(a) of Zn₀.06 Se₀.94 (Eg=2.8eV) to point (b) of Zn₀.2 Mg₀.8 S(Eg=5.0eV), in which the band gap Eg increases as coming nearer towardspoint (b) from (a).

FIG. 5 shows the energy band gaps in GaAs, ZnS, ZnSe, MgS, and MgSecalculated by Harrison's LCAO approximation. It can be appreciated fromFIG. 5 that the difference ΔEc between the minimum levels of theconduction bands and the difference ΔeV between the maximum levels ofthe valence band of ZnSe and MgS are respectively ΔEc=2eV and ΔEv=0.6eV.It can be considered that the increase of the band gap Eg from point (a)towards point (b) in FIG. 4 is distributed into ΔEc and ΔEv at the ratioof approximately 2 : 0.6. For example, if Eg increases by 1eV, theminimum level Ec of the conduction band increases by 1×2 / (2+0.6)=0.77eV.

Although a value of 0.2eV is calculated as the band offset ΔEc betweenZnSe and GaAs according to FIG. 5, a value not more than 0.1eV isobtained experimentally. Therefore, ΔEc between ZnS and GaAs can beapproximated to 0eV. ΔEc between Zns and GaAs also does not take a greatvalue. Therefore, a great error will not be introduced even if ΔEc isapproximated as ΔEc=0 between ZnS₀.06 Se₀.94 and GaAs.

According to the above-described results, the condition of equation (12)is equivalent to Ec in a desired gate insulating film being greater by0.13eV to 0.93eV than that of ZnS₀.06 Se₀.94 at point (a). Consideringthat the distribution of ΔEc and ΔEv is 2 : 0.6 as described above, thecomposition range of a desired gate insulating film has a band gap Eg inthe gate insulating film greater than that of ZnS₀.06 Se₀.94 at point(a) by 0.17eV to 1.2eV. In other words, the composition range of adesired gate insulating film is set to satisfy equation (13).

    3eV≲Eg≲4eV                                 (13)

The composition range that meets equation (13) corresponds to the rangeof point (c) to point (d) on the equivalent lattice constant line 14 ofFIG. 4. The composition of point (c) is Zn₀.95 Mg₀.05 S₀.11 Se₀.89, andthe composition of point (d) is Zn₀.59 Mg₀.41 S₀.52 Se₀.89. If thethickness of the gate insulating film is approximately 400Å, the crystalof the gate insulating film can be grown coherently on the GaAssubstrate even if the lattice constant of approximately 0.6% between theGaAs substrate and the gate insulating film does not match. Therefore, asmall area converting the vicinity of the line from point (c) to point(d) on FIG. 4 is allowable for the composition. Therefore, a MISFET thatcan operate in practice is obtained using the composition ratio meetingthe conditions of equations (14) and (15).

    0.01≲×≲0.4                           (14)

    0≦y≲0.6                                     (15)

It can be easily inferred from FIG. 5 that the maximum level of thevalence band of Zn_(1-x) Mg_(x) S_(y) Se_(1-y) has a great band offsetamount ΔEv with respect to the maximum level of the valence band of GaAsregardless of the composition. Therefore, the composition of Zn_(1-x)Mg_(x) S_(y) Se_(1-y) satisfying equation (12) can be used for the gateinsulating film of a p channel MISFET as well as of an n channel MISFET.

By setting the composition of the gate insulating film on or in thevicinity of the equivalent lattice constant line 14 of FIG. 4, thelattice matching of the gate insulating film with respect to the GaAssubstrate can be made favorable. It can be inferred from FIG. 5 that thegate insulating film having any composition of the AnMgSSe system has aband gap greater than that of GaAs. A II-VI group compound semiconductorZn_(1-x) Mg_(x) S_(y) Se_(1-y) has a small interface state density atthe interface with the GaAs substrate, so that a good gate insulatingfilm can be obtained.

Thus, according to the present invention, (1) the interface statedensity between a gate insulating film and a GaAs substrate can bereduced; (2) a good lattice matching can be obtained between a gateinsulating film and a GaAs substrate; (3) the band gap of a gateinsulating film can be increased to obtain a good gate insulating film;(4) the band offset amount between a GaAs substrate and a gateinsulating film can be increased with respect to both the valence bandand the conduction band. As a result, a practical GaAs-MISFET can beobtained.

By using the GaAs-MISFET of the present invention, a high speed logicalelement can be obtained that can be applied to a great logic voltageswing. Furthermore, a high frequency analog element can be formed thatallows application of a signal of a large voltage swing to a gateelectrode.

Because a p channel type MISFET can be provided as well as an n channeltype MISFET according to the present invention, a complementary typeintegrated circuit can be formed on a GaAs substrate corresponding to aCMOS (Complementary metal Oxide Semiconductor) integrated circuit on asilicon substrate. As a result, a GaAs integrated circuit that canoperate at a high speed with low power consumption can be provided thatwas not obtained by the conventional art.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

We claim:
 1. A MISFET comprising:GaAs substrate, a gate insulating filmof a II-VI group compound including Zn, Mg, S, and Se, epitaxially grownon said substrate, and a gate electrode formed on said gate insulatingfilm.
 2. The MISFET according to claim 1, wherein said gate insulatingfilm is formed of a II-VI group compound of Zn_(1-x) Mg_(x) S_(y)Se_(1-y), with a composition within the range of 0.01≲×≲0.4 and 0≦y≲0.6.3. The MISFET according to claim 1, wherein said gate insulating filmhas a lattice matching said GaAs substrate.
 4. The MISFET according toclaim s, wherein said gate insulating film has a lattice matching saidGaAs substrate.